PCB Factory Planner
GTNH · GT5-Unofficial · MTEPCBFactory

PCB Factory Planner

Circuit Board Fabricator with every knob modeled: machine tier (1–3) gates recipes, nanites drive parallels (⌈count0.75⌉, max 256), cooling upgrades gate overclocking (none → no OC · Liquid Cooling → ×2 imperfect · Thermosink → ×4 perfect), each installed upgrade multiplies power by √(upgrades), and trace size trades speed against board yield and efficiency. TecTech multi-amp hatches supported (1–2 regular or 1 TT).

Recipe

at 100% trace size
must match recipe variant

Machine

Throughput
—
boards / min
Parallels
—
from nanites
Recipe time
—
trace + OC
Power draw
—
incl. efficiency
Boards per craft
—
yield × trace
EU per board
—
vs base
Stock inputs
—
sets per craft, minimum

Throughput vs nanite count

Boards per minute sweeping nanites in the containment bus (log scale), one line per cooling upgrade. Parallels grow as ⌈n0.75⌉ up to 256 — but more parallels eat overclock headroom, so the curves converge when power-limited. Marker = current setting.

Throughput vs trace size

Trace size scales duration by (100/trace)² and board yield by 100/trace: bigger traces are much faster per craft but yield fewer boards — net boards/min still rises with trace until power runs out.

EU per board vs trace size

Bigger traces also drop machine efficiency (10000 × 100/trace), inflating the effective power draw — the energy price of the speed from the chart above.

How the PCB Factory computes this: recipe requires machine tier ≥ recipe tier (T2/T3 need their extra structure) and, for bio recipes, the Bio Chamber. Parallels = min(⌈nanites^0.75⌉, 256) from the matching nanite type in the Nanite Containment Bus; recipes without a nanite variant run 1 parallel. Cooling: without a cooling upgrade the calculator runs setNoOverclock — zero OCs regardless of power. Liquid Cooling enables regular imperfect OCs (×4 power / ×2 speed, 10 L/s distilled water); Thermosink makes them perfect (×4 / ×4, 10 L/s Super Coolant). OC count = ⌊log₄(supply ÷ (EU/t × parallels × √upgrades))⌋, uncapped by tier; surplus past 1 tick becomes sub-tick parallels. Upgrades penalty: EU/t is multiplied by √(upgrades installed) (Bio Chamber and cooling each count). Trace size (50–200%): roughness r = 100 ÷ trace; duration ×r², board output chance ×r, and max efficiency = 10000 × r — so large traces run hot: ×4 faster at 200% but half the boards and double the effective draw. Power: 1–2 regular hatches or 1 TT multi-amp hatch; voltage = average hatch voltage, amps summed (a single regular hatch counts as 1A). Batch mode and input separation supported.